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POWER MANAGEMENT Description
The SC1480A is a single output, constant on-time synchronous-buck, pseudo fixed frequency, PWM controller intended for use in notebook computers and other battery operated portable devices. .eatures include high efficiency and fast dynamic response with no minimum on time, a reference input and a buffered RE.OUT pin capable of sourcing 3mA. The excellent transient response means that SC1480A based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. The SC1480A incorporates two power-reducing states, standby and shutdown. In standby mode, the switcher output is shutdown but the buffered reference output stays up, reducing quiescent current to a low 125A. This is particularly useful for reducing battery draw in systems which implement a suspend-to-RAM (S3) state. The SC1480A can be completely shut down, drawing less than 10A. The integrated gate drivers feature adaptive shootthrough protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, overvoltage and under-voltage protection, and a PGOOD output.
DDR and DDR2 Memory VTT Power Supply Controller
.eatures
K Compatible with DDR & DDR2 memory power requirements K Constant on-time for fast dynamic response K Programmable VOUT based on external reference K VBAT range = 1.8V 25V K DC current sense using low-side RDS(ON) sensing or sense resistor K 3mA reference output buffer K Low power S3 state K Resistor programmable frequency K Cycle-by-cycle current limit K Digital soft start K Output current source-sink capability K Overvoltage/under-voltage fault protection and PGOOD output K Under 10uA typical shutdown current K Low quiescent power dissipation K 14 Lead TSSOP K Industrial temperature range K Integrated gate drivers with soft switching K Efficiency >80%
SC1480A
Applications
K K K K K
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
Typical Application Circuit
VDDQ VBAT 5VSUS 5VRUN VBAT
R1 10k0
R2 RTON
R3
R4 D1 10R U1 1 2 REFIN TON REFOUT VCCA FB PGD VSSA SC1480A BST DH LX ILIM VDDP DL PGND 14 13 12 11 Q2 10 9 8 C5 1u R5 RLIM + C4 C1 0u1 Q1 C2 10u L1 VTT
REFOUT
3 C3 4 1u 5 6 7 C8 0u1 R6 10k0 C6 1n R7 10R C7 1u
VTT PGOOD
Revision: December 8, 2004
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SC1480A
POWER MANAGEMENT Absolute Maximum Ratings(3)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Pin Combination TON to VSSA DH, BST to PGND LX to PGND VSSA to PGND BST to LX DL, ILIM, VDDP to PGND FB, PGD, REFIN, REFOUT, VCCA to VSSA VCCA to FB, PGD, REFIN, REFOUT Thermal Resistance, Junction to Ambient(4) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V V C/W C C C
JA TJ TSTG TLEAD
100 -40 to +125 -65 to +150 300
Electrical Characteristics
Test Conditions: VBAT = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies VCCA Input Voltage VDDP Input Voltage VBAT Input Voltage VDDP Operating Current VCCA Operating Current VCCA Standby Current TON Operating Current REFIN Bias Current Shutdown Current (REFIN = 0V) FB > regulation point, ILOAD = 0A FB > regulation point, ILOAD = 0A VDDP < VDDP UV Threshold No Load On REFOUT RTON = 1M, VBAT = 25V REFIN = 1.25V REFIN VC C A VD D P TON, VBAT = 25V
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5.0 5.0 25 75 700 125 24
4.5 4.5
5.5 5.5
V V V
160 1100
A A A A
1 0 5 5 0 1 10 10 1
A A A A A
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SC1480A
POWER MANAGEMENT Electrical Characteristics Cont.
Test Conditions: VBAT = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Controller Error Comparator Threshold (FB Turn-on Threshold) (1) On-Time VCCA = 4.5V to 5.5V RTON = 1M RTON = 500k Minimum Off Time FB Input Resistance Over-Current Sensing ILIM Sink Current Current Comparator Offset Reference Buffer REFOUT Source Current REFIN Enable Threshold REFIN Enable Hysteresis REFOUT DC Accuracy Fault Protection Current Limit (Positive) (2) PGND-LX, RILIM = 5k PGND-LX, RILIM = 10k PGND-LX, RILIM = 20k Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault Over-Voltage Fault Delay PGD Low Output Voltage PGD Leakage Current PGD UV Threshold PGND-LX With respect to REFOUT With respect to REFOUT FB forced above OV threshold Sink 1mA FB in regulation, PGD = 5V With respect to REFOUT -10 -15 50 100 200 -125 -20 +10 5 0.4 1 -8 35 80 170 -160 -28 +8 65 120 230 -90 -15 +12 mV mV mV mV % % s V A % No load, REFIN = 1.25V 1.240 REFIN rising 0.50 30 1.260 1.238 1.262 3 0.60 mA V mV mV DL high PGND - ILIM 10 9 -10 11 +10 A mV REFOUT 1660 913 400 500 REFOUT REFOUT -10 +10 1411 776 1909 1050 550 mV ns ns ns k
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SC1480A
POWER MANAGEMENT Electrical Characteristics Cont.
Test Conditions: VBAT = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Fault Protection (Cont.) PGD Fault Delay VCCA Under Voltage Threshold VDDP Under Voltage Threshold VDDP Under Voltage Hysteresis Over Temperature Lockout Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Shoot-Through Delay(6) DL Pull-Down Resistance DL Pull-Up Resistance DH Pull-Down Resistance DH Pull-Up Resistance(7) DL Sink Current DL Source Current DH Sink/Source Current DH or DL rising DL low DL high DH low, BST - LX = 5V DH high, BST - LX = 5V VDL = 2.5V VDL = 2.5V VDH = 2.5V 30 0.8 2 2 2 3.1 1.3 1.3 1.6 4 4 4 ns A A A REFIN high to PGD high REFIN high to UV high 440 440 clks(5) clks(5) 10C Hysteresis FB forced outside PGD window Falling (100mV hysteresis) Falling 5 4.0 3.5 250 165 3.7 4.3 s V V mV C
Notes: (1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOS.ET. (3) This device is ESD sensitive. Use of ESD handling precautions is required. (4) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7. (5) clks = switching cycles. (6) Guaranteed by design. Please see Shoot-Through Delay Timing Diagram on Page 5. (7) Semtechs SmartDriverTM .ET drive first pulls DH high with a pull-up resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typ.).
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SC1480A
POWER MANAGEMENT Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
Block Diagram
VCCA (4) REFIN (1)
POR / SS
OT
REF BUFFER TON (2) TON ON OFF PWM TOFF CONTROL LOGIC
VDDP BST (14) DH (13) LX (12)
HI
OC ISENSE REFOUT (3) + VDDP (10) FB (5) + PGD (6) OV VSSA (7) FAULT MONITOR UV REF + 10% REF - 10% REF - 20% LO DL (9) PGND (8) ZERO I ILIM (11)
.IGURE 1: Block Diagram
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SC1480A
POWER MANAGEMENT Pin Configuration
TOP VIEW
REFIN TON REFOUT VCCA FB PGD VSSA 1 2 3 4 5 6 7 14 13 12 11 10 9 8 BST DH LX ILIM VDDP DL PGND
Ordering Information
Device
(1)
P ackag e TSSOP-14 Evaluation Board
SC1480AITSTRT(2) S C 1480A E V B
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE, RoHS and J-STD-020B compliant.
(14 Pin TSSOP)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name REFIN TON REFOUT VC C A FB PGD VSSA PGND DL VD D P ILIM LX DH BST Pin Function Reference input. A 10kOhm + 10kOhm resistor divider from VDDQ to VSSA sets this voltage. A 0.1F input filter capacitor is recommended. This pin is used to sense VBAT through a pull-up resistor, RTON, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA. Buffered REFIN output. The switching controller regulates to this voltage. Connect a series 10 Ohm and 1F from this pin to VSSA. Supply voltage input for the analog supply. Use a 10 Ohm/1F RC filter from 5VSUS to VSSA. Feedback input. Connect to the output at the output capacitor. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. Ground reference for analog circuitry. Connect to bottom of the output capacitor(s). Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Decouple this pin with a 1F ceramic capacitor to PGND. Current limit input pin. Connect to drain of low-side MOSFET for RDS(ON) sensing or the source for resistor sensing through a threshold sensing resistor. Phase node (junction of top and bottom MOSFETs and the output inductor) connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive.
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SC1480A
POWER MANAGEMENT Applications Information
+5V Bias Supplies The SC1480A requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951. .or optimal operation, the controller has its own ground reference, VSSA, which should be tied by a single trace to PGND at the negative terminal of the output capacitor (see Layout Guidelines). All external components referenced to VSSA in the Typical Applications Circuit on Page 1 should be connected to VSSA. The supply decoupling capacitor should be tied directly between the VCCA and VSSA pins. A 10 resistor should be used to decouple VCCA from the main 5V supply, which may or may not be the same 5V supply that powers VDDP. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, VSSA must be connected to the PGND plane at the negative terminal of the output capacitor(s) only. The VDDP input provides power to the upper and lower gate drivers. A decoupling capacitor is required. No series resistor between VDDP and 5V is required. See layout guidelines for more details. Pseudo-fixed .requency Constant On-Time PWM Controller The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see .igure 1, SC1480A Block Diagram). The output ripple voltage developed across the output filter capacitors ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (tON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage-proportional current is used to charge
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an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need for a clock generator. .or VOUT < 3.3V:
V t ON = 3.3 x10 -12 * (R TON + 37 x10 3 ) * OUT + 50ns V BAT
RTON is a resistor connected from the input supply (VBAT) to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1n. ceramic capacitor. Enabling RE.IN enables the RE.OUT buffered reference (assuming VCCA is present) and VDDP enables the VTT output (assuming VCCA and RE.IN are present). It is usual to use a resistor divider from VDDQ to generate RE.IN, so if VDDQ is not present, neither RE.OUT nor VTT will be present. .or S3 mode, VDDP may be removed, disabling VTT but leaving RE.OUT present. Current Limit Circuit Current limiting of the SC1480A can be accomplished in two ways. The on-state resistance of the low-side MOS.ETs can be used as the current sensing element or sense resistors in series with the low-side sources can be used if greater accuracy is desired. R DS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistors between the ILIM pin and LX pin set the over current threshold. This resistor R ILIM is connected to a 10A current source within the SC1480A which is turned on when the low side MOS.ET turns on. When the voltage drop across the sense resistor or low side MOS.ET equals the voltage across the RILIM resisor, positive current limit will activate. The high side MOS.ET will not be turned on until the voltage drop across the sense element (resistor or MOS.ET) falls below the voltage across the RILIM resistor. In an extreme overcurrent situation, the top MOS.ET will never turn back on and eventually the part will latch off due to output undervoltage (see Output Undervoltage Protection).
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SC1480A
POWER MANAGEMENT Applications Information (Cont.)
The current sensing circuit actually regulates the inductor valley current (see .igure 2). This means that if the current limit is set to 3A, the peak current through the inductor would be 3A plus the peak ripple current, and the average current through the inductor would be 3A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below: In this case, when the bottom MOS.ET is turned on, the phase node, LX, will be higher than PGND initially. The SC1480A monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom.) the bottom MOS.ET is turned off. The device then waits for approximately 2s and then DL goes high for 300ns (typ.) once more to sense the current. This repeats until either the over-current condition goes away or the part latches off due to output overvoltage (see Output Overvoltage Protection). Power Good Output (VTT)
IPEAK
ILOAD ILIMIT
The ower good is an open-drain output and requires a pull-up resistor. When the output voltage is 10% above or below its set voltage (RE.OUT), PGD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGD is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5s delay built into the PGD circuitry to prevent false transitions. Output Overvoltage Protection (VTT) When the output exceeds 10% of the its set voltage (RE.OUT) the low-side MOS.ET is latched on. It stays latched on and the controller is latched off until reset (see below). There is a 5s delay built into the OV protection circuit to prevent false transitions. Note: to reset VTT from any fault, VCCA or RE.IN must be toggled. Output Undervoltage Protection (VTT) When the output is 20% below its set voltage (RE.OUT) the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset (see below). There is a 5s delay built into the UV protection circuit to prevent false transitions. Note: to reset VTT from a any fault, VCCA or RE.IN must be toggled. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and also inhibits the RE.OUT buffer. When VCCA rises above 4.2V, the VCCA UVLO circuitry enables the RE.OUT buffer, resets the fault latch and soft start timer, and
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INDUCTOR CURRENT
TIME Valley Current-Limit Threshold Point
.igure 2: Valley Current Limiting The equation for the current limit threshold is as follows:
ILIMIT = 10e -6 *
RILIM A R SENSE
Where (referring to .igure 3 on Page 14) RILIM is R5 and RSENSE is the RDS(ON) of the bottom .ET of Q1. .or resistor sensing, a sense resistor is placed between the source of the bottom .ET of Q1 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across R ILIM , a positive over-current exists and the high side MOS.ET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor. The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND through the inductor and bottom MOS.ET).
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SC1480A
POWER MANAGEMENT Applications Information (Cont.)
allows switching to occur, if enabled (see below). When RE.IN rises above the RE.IN threshold, RE.OUT will start to rise. The switching controller is enabled by two things: RE.IN being greater than the RE.IN threshold and VDDP being greater than the VDDP UVLO of 3.3V, above which switching will commence (assuming VCCA is present). Switching always starts with DL to charge up the BST capacitor. With the softstart circuit (automatically) enabled, the SC1480A will progressively limit the VTT output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time 2) 110 cycles at 50% ILIM with normal minimum off-time 3) 110 cycles at 75% ILIM with normal minimum off-time 4) 110 cycles at 100% ILIM with normal minimum off-time. At this point the output undervoltage and power good circuitry is enabled. If VDDP falls below 3.5V (nom.) the VTT regulator will shut down. If RE.IN falls below the RE.IN threshold, RE.OUT and VTT will shut down. There is 100mV of hysteresis built into the VCCA UVLO circuit and when VCCA falls to 4.1V (nom.) the output drivers are shut down and tristated and the RE.OUT buffer shut down and disabled. MOS.ET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOS.ETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOS.ET from turning on until DL is fully off (below ~1V). Conversely, it monitors the phase node, LX, to determine the state of the high side MOS.ET, and prevents the low-side MOS.ET from turning on until DH is fully off (LX below ~1V). Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOS.ET. DDR Reference Buffer The reference buffer is capable of driving 3mA and sinking 25A. Since the output is class A, if additional sinking is required an external pulldown resistor can be added. Make sure that the ground side of this pulldown is tied to VSSA. As with most opamps, a small resistor is required when driving a capacitive load. To ensure stability use either a 10 resistor in series with a 1. capacitor or a
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100 resistor in series with a 0.1. capacitor from RE.OUT to VSSA. Since it is possible to have as much as 10. to 20. of capacitance at the memory socket or on-board the DIMMs, it is recommended that a 0 resistor is placed between RE.OUT and the DIMM sockets. This allows the addition of extra resistance between RE.OUT and the DIMMs to avoid spurious OVP at startup, which can occur if RE.OUT rises really slowly and VTT overshoots it. The extra resistance allows RE.OUT to rise faster, avoiding this issue. RE.IN should also be filtered so that VDDQ ripple does not appear at the RE.IN pin. If a resistor divider is used to create RE.IN from VDDQ, then a 0.1. capacitor from RE.IN to VSSA will provide adequate filtering. VTT Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. .or best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY =
t ON( MIN ) t ON( MIN )
+ t OFF(MAX )
Be sure to include inductor resistance and MOS.ET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC1480A System DC Accuracy (VTT) Two IC parameters effect system DC accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. The SC1480A regulates to the RE.OUT voltage not the RE.IN voltage. Since DDR specifications are written with respect to RE.OUT, the offset of the reference buffer does not create a regulation error. The error comparator offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy.
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SC1480A
POWER MANAGEMENT Applications Information (Cont.)
The on pulse in the SC1480A is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. .or example, if RE.OUT=0.9V, then the valley of the output ripple will be 0.9V. If the ripple is 20mV with VBAT = 6V, then the DC output voltage will be 0.91V. If the ripple is 30mV with VBAT = 25V, then the DC output voltage will be 0.915V. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency. Switching frequency variation with load can be minimized by choosing MOS.ETs with lower R DS(ON). High R DS(ON) MOS.ETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. Input (VBAT) Supply Selection The SC1480A can be configured so that VTT is generated directly from the battery. Alternatively, VTT can be generated from VDDQ. Since the battery configuration generally yields better overall efficiency and performance, the recommended method is to generate VTT from the battery. Design Procedure Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. .or purposes of demonstrating the procedure the VTT output for the schematic in .igure 3 on Page 14 will be designed. The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (VBAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. .or the purposes of this design example we will use a VBAT range of 8V to 20V. .our parameters are needed for the output: 1) nominal output voltage, VOUT (for DDR2 this is 0.9V) 2) static (or DC) tolerance, TOL ST (for DDR2 this is
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+/-40mV, or 4.44%, we will design for 4%) 3) transient tolerance, TOLTR and size of transient (for DDR2 this is undefined, so assume +/-8% for purposes of this demonstration). 4) maximum output current, IOUT (we will design for 3A) Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOS.ETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOS.ET switches usually dictates where the design ends up. A default R tON value of 715k is suggested as a starting point, but this is not set in stone. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and RtON. .or VOUT < 3.3V:
VOUT -9 t ON _ VBAT (MIN) = 3.3 * 10 -12 * (R tON + 37 * 10 3 ) * + 50 * 10 s VBAT (MIN)
.rom this value of t ON we can calculate the nominal switching frequency as follows:
fSW _ VBAT (MIN ) =
and
VOUT Hz (VBAT (MIN) * t ON _ VBAT (MIN) )
fSW _ VBAT (MAX ) =
VOUT Hz (VBAT(MAX ) * t ON _ VBAT(MAX ) )
tON is generated by a one-shot comparator that samples VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3p. capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. .or our DDR2 VTT example we select RtON = 715k: tON_VBAT(MIN) = 329ns and tON_VBAT(MAX) = 162ns fSW_VBAT(MIN) = 342kHz and fSW_VBAT(MAX) = 278kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place.
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SC1480A
POWER MANAGEMENT Applications Information (Cont.)
L VBAT (MIN ) = (VBAT (MIN ) - VOUT ) *
and
t ON _ VBAT (MIN)
OUT
(0.5 * I )
H
the DC error. The DC error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feedback resistors. .or our DDR2 VTT example:
L VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
.or our DDR2 VTT example:
t ON _ VBAT (MAX )
(0.5 * I )
OUT
H
ERRST = 36mV and ERRDC = 18mV, therefore RESR_ST(MAX) = 26m
LVBAT(MIN) = 1.6H and LVBAT(MAX) = 2.1H We will select an inductor value of 2.2H to reduce the ripple current, which can be calculated as follows:
RESR _ TR (MAX ) =
(ERR
TR
- ERRDC )
I IOUT + RIPPLE _ VBAT (MAX ) 2
Ohms
IRIPPLE _ VBAT (MIN ) = (VBAT (MIN ) - VOUT ) *
and
t ON _ VBAT (MIN ) L
A P -P
Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. .or half of full load, divide the IOUT term by 2. .or our DDR2 VTT example:
IRIPPLE _ VBAT (MAX ) = (VBAT (MAX ) - VOUT ) *
.or our DDR2 VTT example:
t ON _ VBAT (MAX ) L
A P -P
ERRTR = 72mV and ERRDC = 18mV, therefore RESR_TR(MAX) = 14.6m for a 3A load transient We will select a value of 15m maximum for our design. Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows:
IRIPPLE_VBAT(MIN) = 1.06AP-P and IRIPPLE_VBAT(MAX) = 1.4AP-P .rom this we can calculate the minimum inductor current rating for normal operation:
IINDUCTOR (MIN ) = IOUT (MAX ) +
IRIPPLE _ VBAT (MAX ) 2
A (MIN )
.or our DDR2 VTT example: IINDUCTOR(MIN) = 3.7A(MIN) Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R ESR_ST(MAX) ) and transient ESR (R ESR_TR(MAX)):
RESR (MIN ) =
3 2 * * COUT * fSW
This criteria should be checked once the output capacitance has been determined. Now that we know the output ESR we can calculate the output ripple voltage:
VRIPPLE _ VBAT(MAX ) = RESR * IRIPPLE _ VBAT(MAX ) VP -P
and
Ohms IRIPPLE _ VBAT (MAX ) Where ERRST is the static output tolerance and ERRDC is
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RESR _ ST (MAX ) =
(ERR
ST
- ERRDC ) * 2
VRIPPLE _ VBAT (MIN) = RESR * IRIPPLE _ VBAT (MIN) VP -P .or our DDR2 VTT example:
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SC1480A
POWER MANAGEMENT Applications Information (Cont.)
VRIPPLE_VBAT(MAX) = 21mVP-P and VRIPPLE_VBAT(MIN) = 16mVP-P Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VOUT, should be approximately 15mVP-P at minimum V BAT , and worst case no smaller than 10mV P-P . If VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs: capacitor. Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage:
IIN(RMS ) = VOUT * (VBAT (MIN ) - VOUT ) *
.or our DDR2 VTT example: IIN(RMS) = 0.95ARMS
IOUT VBAT _ MIN
A RMS
VOUT _ ST _ POS = VOUT + ERRDC V
.or our DDR2 VTT example: VOUT_ST_POS = 0.918V
POSLIM TR = VOUT * TOL TR V
Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10., 1210 size, 25V ceramic capacitor can handle up to 3ARMS. Refer to manufacturers data sheets. .inally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the valley current, which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOS.ET RDS(ON) at VGS = 4.5V for purposes of this calculation:
Where TOLTR is the transient tolerance. .or our DDR2 VTT example: POSLIMTR = 1.972V The minimum output capacitance is calculated as follows:
I IOUT + RIPPLE _ VBAT (MAX ) 2 F =L* 2 2 POSLIM TR - VOUT _ ST _ POS
2
IVALLEY = IOUT -
IRIPPLE _ VBAT (MIN ) 2
A
The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
RILIM = (IVALLEY * 1.2) *
RDS( ON) * 1.4 10 * 10 - 6
Ohms
C OUT (MIN)
(
)
.or our DDR2 VTT example: IVALLEY = 2.47A and RILIM = 9.12k We select the next lowest 1% resistor value: 9.09k Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be calculated by substituting the desired current for the IOUT term. .or our DDR2 VTT example: COUT(MIN) = 295.. We will select 220., using one 220., 15m
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SC1480A
POWER MANAGEMENT Applications Information (Cont.)
TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
PD = VCCA * IVCCA + Vg * Q g * f
W
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = .ET gate charge, from the .ET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: TA = 85C JA = 100C/W VCCA = 5V IVCCA = 1100A (data sheet maximum) Vg = 5V Qg = 60nC f = 342kHz gives us:
PD = 5 * 1100 * 10 -6 + 5 * 60 * 10 -9 * 342 * 103 = 0.108 W
and
TJ = 85 + 0.108 * 100 = 95 .8 C
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
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SC1480A
POWER MANAGEMENT Application Information (Cont.)
Layout Guidelines One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All components that are referenced to VSSA should connect to it locally at the chip. VSSA should connect to power ground at the output capacitor(s) only. .eedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run them in a quiet layer if possible. Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and connected directly to them on the same side. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use minimum land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOS.ETs to reduce parasitic impedances (and MOS.ET switching losses), the low-side MOS.ET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer Current sense connections must always be made using Kelvin connections to ensure an accurate signal. We will examine the SC1480A DDR2 reference design used in the Design Procedure section while explaining the layout guidelines in more detail.
VDDQ VBAT 5VSUS 5VRUN VBAT
R1 10k0 0402
R2 715k 0402
R3 470k 0402
R4 10R 0402 1 2 U1 REFIN TON REFOUT VCCA FB PGD VSSA SC1480A BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 C10 1u 0603
SOD323 D1 C5
Q1 5 FDS6982S
6 C4 2n2 0402 C3 0u1 0603 C1 10u 1210
0u1 0603 4 3
REFOUT
3 C2 4 1u 0402 5 6 7 C7 0u1 0402 R6 10k0 0402 C8 1n 0402 R7 10R 0402 C9 1u 0603
L1 8 R 5 9k09 0402 2 7 2525
2u2 VTT C6 + 220u/15mOhm 7343
VTT PGOOD
1
R8 0R 0402
.igure 3: Reference Design and Layout Example for VBAT = 8V to 20V, VTT = 0.9V, 3A Note R8 is present to facilitate isolation of power ground and VSSA during layout.
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SC1480A
POWER MANAGEMENT Application Information (Cont.)
The layout can be considered in two parts, the control section referenced to VSSA and the power section. Looking at the control section first, locate all components referenced to VSSA on the schematic and place these components at the chip. Connect VSSA using either a wide (>0.020) trace or a copper pour if room allows. Very little current flows in the chip ground therefore large areas of copper are not needed.
5VRUN
U1 1 2 3 C2 4 1u 0402 5 6 7 C7 0u1 0402 R6 10k0 0402 C8 1n 0402 R7 10R 0402 C9 1u 0603 REFIN TON REFOUT VCCA FB PGD VSSA
SC1480A BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 C10 1u 0603
.igure 4: Components Connected to VSSA
.igure 5: Example VSSA 0.020 Trace In .igure 5 above, all components referenced to VSSA have been placed and connected using a 0.020 trace. Decoupling capacitors C9 and C10 are as close as possible to their pins. C10 should connect to the PGND plane using two vias.
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SC1480A
POWER MANAGEMENT Application Information (Cont.)
As shown below, .B and VSSA should be routed as a differential pair to the output capacitor.
U1 1 2 3 C2 4 1u 0603 5 6 7 C7 0u1 0402 R6 10k0 0402 C8 1n 0402 R7 10R 0402 C9 1u 0603 REFIN TON REFOUT VCCA FB PGD VSSA SC1480A BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 C6 9 8 R8 0R 0402 + 220u/15mOhm 7343 VTT
VSSA FB
.igure 6: Differential Routing of .eedback and Ground Reference Traces Next, looking at the power section, the schematic in .igure 7 below shows the power section. The highest di/dts occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible.
VBAT
Q1 FDS6982S
5
6 C4 2n2 0402 C3 0u1 0603 C1 10u 1210
4 3 L1 8 7 2525 + 2 220u/15mOhm 7343 1 R8 0R 0402 C6 2u2 VTT
.igure 7: Power Section and Input Loop The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize parasitics and losses. See .igure 8 on Page 17 for an example.
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SC1480A
POWER MANAGEMENT Application Information (Cont.)
.igure 8: Power Section Component Placement and Copper Pours Key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) Notice in .igure 8 above placement of 0 resistor at the bottom of the output capacitor to connect to VSSA. 5) The current limit resistor should be placed as close as possible to the ILIM and LX pins. Connecting the control and power sections should be accomplished as follows (see .igure 9 on Page 18): 1) Route VSSA and .B feedback traces as a differential pair routed in a quiet layer away from noise sources. 2) Route DL, DH and LX (low side .ET gate drive, high side .ET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane.
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SC1480A
POWER MANAGEMENT Application Information (Cont.)
Q1 FDS6982S U1 1 2 3 4 5 6 7 REFIN TON REFOUT VCCA FB PGD VSSA SC1480A BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 2 4 3 L1 8 7 2525 2u2 5 6
.igure 9: Connecting Control and Power Sections Phase node (black) to be copper pours (preferred) or wide copper traces. Gate drive traces (red) and phase node trace (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
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SC1480A
POWER MANAGEMENT Typical Characteristics
Efficiency vs. Output Current vs. Input Voltage
100 90 80 70 Efficiency (%) VOUT (V) 60 50 40 30 0.890 20 10 0 0.0 0.5 1.0 1.5 IOUT (A) 2.0 2.5 3.0 0.885 0.880 0.0 0.5 1.0 1.5 IOUT (A) 2.0 2.5 3.0 0.905 0.900 VBAT = 8V 0.895 VBAT = 20V VBAT = 8V 0.920 0.915 0.910 VBAT = 20V
Output Voltage vs. Output Current vs. Input Voltage
Switching .requency vs. Output Current vs. Input Voltage
400 VBAT = 8V 350 300 Frequency (kHz) 250 VBAT = 20V 200 150 100 50 0 0.0 0.5 1.0 1.5 IOUT (A) 2.0 2.5 3.0
Please refer to .igure 3 on Page 14 for test schematic
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SC1480A
POWER MANAGEMENT Typical Characteristics (Cont.)
VTT Load Transient Response, 0A to 3A to 0A Trace 1: VTT, 50mV/div., AC coupled Trace 2: LX, 20V/div. Trace 3: not connected Trace 4: load current, 2A/div Timebase: 40s/div. VBAT = 8V
VTT Load Transient Response, 3A to 0A Zoomed Trace 1: VTT, 50mV/div., AC coupled Trace 2: LX, 20V/div. Trace 3: not connected Trace 4: load current, 2A/div Timebase: 10s/div. VBAT = 8V
VTT Load Transient Response, 0A to 3A Zoomed Trace 1: VTT, 20mV/div., AC coupled Trace 2: LX, 20V/div. Trace 3: not connected Trace 4: load current, 2A/div Timebase: 4s/div. VBAT = 8V
Please refer to .igure 3 on Page 14 for test schematic
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SC1480A
POWER MANAGEMENT Typical Characteristics (Cont.)
Startup, RE.IN Going 0V to 0.9V Trace 1: VTT, 0.5V/div. Trace 2: LX, 20V/div. Trace 3: RE.OUT, 1V/div. Trace 4: RE.IN, 1V/div. Timebase: 400s/div. VBAT = 8V
Startup, RE.IN Going 0V to 0.9V Showing PGD Trace 1: VTT, 0.5V/div. Trace 2: LX, 20V/div. Trace 3: RE.OUT, 1V/div. Trace 4: PGD, 5V/div. Timebase: 400s/div. VBAT = 8V
Please refer to .igure 3 on Page 14 for test schematic
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SC1480A
POWER MANAGEMENT Marking Diagram Top Mark Bottom Mark
yy = two-digit year of manufacture ww = two-digit week of manufacture
xxxxxx = Wafer Lot Number xx = Assembly Lot Number
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SC1480A
POWER MANAGEMENT Outline Drawing - TSSOP-14
Land Pattern - TSSOP-14
Contact Information
Semtech Corporation Power Management Products Division 200 .lynn Road, Camarillo, CA. 93012 Phone: (805)498-2111 .AX (805)498-3804
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